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NBSG14_06 Datasheet, PDF (1/13 Pages) ON Semiconductor – 2.5V/3.3V SiGe Differential 1:4 Clock/Data Driver with RSECL Outputs | |||
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NBSG14
2.5V/3.3V SiGe Differential
1:4 Clock/Data Driver with
RSECL* Outputs
*Reduced Swing ECL
Description
The NBSG14 is a 1âtoâ4 clock/data distribution chip, optimized for
ultraâlow skew and jitter.
Inputs incorporate internal 50 W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
Features
⢠Maximum Input Clock Frequency up to 12 GHz Typical
⢠Maximum Input Data Rate up to 12 Gb/s Typical
⢠30 ps Typical Rise and Fall Times
⢠125 ps Typical Propagation Delay
⢠RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
⢠RSNECL Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = â2.375 V to â3.465 V
⢠RSECL Output Level (400 mV PeakâtoâPeak Output),
Differential Output
⢠50 W Internal Input Termination Resistors
⢠Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
⢠PbâFree Packages are Available
http://onsemi.com
MARKING DIAGRAMS*
FCBGAâ16
BA SUFFIX
CASE 489
QFNâ16
MN SUFFIX
CASE 485G
SG
14
ALYW
ÃÃ1 ÃÃ16 ÃÃ
SG14
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbâFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
July, 2006 â Rev. 9
Publication Order Number:
NBSG14/D
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