NBSG111 Datasheet, PDF (1/11 Pages) ON Semiconductor – 2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver with RSECL Outputs

NBSG111
2.5V/3.3V SiGe Differential
1:10 Clock/Data Driver
with RSECL* Outputs
*Reduced Swing ECL
Description
The NBSG111 is a 1−to−10 differential clock/data driver. The
device is functionally equivalent to the LVEP111 device with much
higher bandwidth and lower EMI capabilities.
Inputs incorporate internal 50 W termination resistors (input to VT
pad) and accept NECL (Negative ECL), PECL (Positive ECL),
LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced
Swing ECL), 400 mV.
The Q[0:9] / Q[0:9] outputs have a differential synchronous enable
(EN/EN) pin. The synchronous enable pin is used to avoid a runt clock
pulse when the device is enabled/disabled as can happen with an
asynchronous control. The internal flip flop is clocked on the falling
edge of selected clock (CLK0/CLK0 or CLK1/CLK1), therefore all
associated specification limits are referenced to the negative edge of
the selected clock input.
The V_BB and V_MM pins are internally generated voltage supplies
available to this device only. The V_BB is used for single−ended NECL
or PECL inputs and the V_MM pin is used for LVCMOS inputs. For
single−ended input operation, the unused differential input is
connected to V_BB or V_MM as a switching reference voltage. V_BB or
V_MM may also rebias AC coupled inputs. When used, decouple V_BB
and V_MM via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB and V_MM outputs should be left open.
Features
• Maximum Input Clock Frequency > 6 GHz Typical
• Maximum Input Data Rate > 6 Gb/s Typical
• 300 ps Typical Propagation Delay
• 60 ps Typical Rise and Fall Times
• RSPECL Output with Operating Range: V_CC = 2.375 V to
3.465 V with V_EE = 0 V
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V_CC = 0 V with V_EE = −2.375 V to −3.465 V
• RSECL Output Level (400 mV Peak−to−Peak Output), Differential
Output
• 50 W Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP and EP Devices
• V_BB and V_MM Reference Voltage Output
http://onsemi.com
MARKING
DIAGRAM*
SG
111
LYW
FCBGA−49
BA SUFFIX
CASE 489A
SG111
L
Y
W
= Device Code
= Wafer Lot
= Year
= Work Week
*For further details, refer to Application Note
AND8002/D
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
1
January, 2007 − Rev. 8
Publication Order Number:
NBSG111/D