NB7V52M Datasheet, PDF (1/10 Pages) ON Semiconductor – 1.8V / 2.5V Differential D Flip-Flop w/ Reset and CML Outputs

NB7V52M
1.8V / 2.5V Differential D
Flip-Flop w/ Reset and CML
Outputs
Multi−Level Inputs w/ Internal Termination
Description
The NB7V52M is a 10 GHz differential D flip−flop with a
differential asynchronous Reset. The differential D/D, CLK/CLK and
R/R inputs incorporate dual internal 50 W termination resistors and
will accept LVPECL, CML, LVDS logic levels.
When Clock transitions from logic Low to High, Data will be
transferred to the differential CML outputs. The differential Clock
inputs allow the NB7V52M to also be used as a negative edge
triggered device.
The 16 mA differential CML outputs provide matching internal
50 W termination and produce 400 mV output swings when externally
receiver terminated with a 50 W resistor to V_CC.
The NB7V52M is offered in a low profile 3 mm x 3 mm 16−pin
QFN package. The NB7V52M is a member of the GigaComm™
family of high performance clock products. Application notes,
models, and support documentation are available at
www.onsemi.com.
Features
• Maximum Input Clock Frequency > 10 GHz
• Maximum Input Data Rate > 10 Gb/s
• Random Clock Jitter < 0.8 ps RMS, Max
• 200 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak, Typical
• Operating Range: V_CC = 1.71 V to 2.625 V with V_EE = 0 V
• Internal 50 W Input Termination Resistors
• QFN−16 Package, 3mm x 3mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7V
52M
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
D
VTD
D Flip−Flop
Q
VTCLK
Q
CLK
CLK
RESET
VTCLK
VTR R R VTR
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
September, 2009 − Rev. 3
Publication Order Number:
NB7V52M/D