NB7LQ572 Datasheet, PDF (1/12 Pages) ON Semiconductor – 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 LVPECL Clock/Data Fanout / Translator

NB7LQ572
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 LVPECL Clock/Data
Fanout / Translator
Multi−Level Inputs w/ Internal Termination
The NB7LQ572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock / Data fanout buffer that
operates up to 7 GHz / 11 Gbps respectively with a 2.5 V or 3.3 V
power supply.
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB7L572, which is pin−compatible to the NB7LQ572.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB7LQ572 incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
LVPECL output copies of Clock or Data. As such, the NB7LQ572 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The two differential LVPECL outputs will swing 750 mV when
externally loaded and terminated with a 50 W resistor to V_CC – 2 V
and are optimized for low skew and minimal jitter.
The NB7LQ572 is offered in a low profile 5x5 mm 32−pin QFN
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB7LQ572 is a member of the GigaComm™ family of high
performance clock products.
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
Q572
AWLYYWWG
G
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Features
• Input Data Rate > 11 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 7 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Fixed Input Equalization
• Low Skew 1:2 LVPECL Outputs, < 15 ps max
• 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML
LVDS
• 160 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 800 mV peak−to−peak,
typical
• Operating Range: 2.5 $5% or 3.3 V $10%
• Internal 50 W Input Termination Resistors
• V_REFAC Reference Output
• QFN−32 Package, 5mm x 5mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2010
1
April, 2010 − Rev. 0
Publication Order Number:
NB7LQ572/D