|
NB7L72M Datasheet, PDF (1/8 Pages) ON Semiconductor – Multi−Level Inputs w/ Internal Termination | |||
|
NB7L72M
2.5V / 3.3V Differential 2 x 2
Crosspoint Switch with
CML Outputs Clock/Data
Buffer/Translator
MultiâLevel Inputs w/ Internal Termination
Description
The NB7L72M is a high bandwidth, low voltage, fully differential
2 x 2 crosspoint switch with CML outputs. The NB7L72M design is
optimized for low skew and minimal jitter as it produces two identical
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, the NB7L72M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
The differential IN/IN inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels (see
Figure 11). The 16 mA differential CML outputs provide matching
internal 50 W terminations and produce 400 mV output swings when
externally terminated with a 50 W resistor to VCC (see Figure 9).
The NB7L72M is the 2.5 V/3.3 V version of the and NB7V72M and
is offered in a low profile 3x3 mm 16âpin QFN package. Application
notes, models, and support documentation are available at
www.onsemi.com.
The NB7L72M is a member of the GigaComm⢠family of high
performance clock products.
Features
⢠Maximum Input Data Rate > 10 Gb/s
⢠Data Dependent Jitter < 10 ps pkâpk
⢠Maximum Input Clock Frequency > 7 GHz
⢠Random Clock Jitter < 0.5 ps RMS, Max
⢠150 ps Typical Propagation Delay
⢠30 ps Typical Rise and Fall Times
⢠Differential CML Outputs, 400 mV peakâtoâpeak, typical
⢠Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
⢠Internal 50 W Input Termination Resistors
⢠QFNâ16 Package, 3mm x 3mm
⢠â40°C to +85°C Ambient Operating Temperature
⢠These are PbâFree Devices
http://onsemi.com
1
QFNâ16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
72M
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbâFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
+
SEL0
IN0
VT0
IN0
0 Q0
1 Q0
IN1
0 Q1
VT1
IN1 +
SEL1
1 Q1
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
1
September, 2008 â Rev. 1
Publication Order Number:
NB7L72M/D
|
▷ |