NB7L572 Datasheet, PDF (1/9 Pages) ON Semiconductor – 2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator

NB7L572
2.5V / 3.3V Differential 4:1
Mux Input to 1:2 LVPECL
Clock/Data Fanout /
Translator
Multi−Level Inputs w/ Internal Termination
The NB7L572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer. The
INx/INx inputs includes internal 50 W termination resistors and will
accept differential LVPECL, CML, or LVDS logic levels. The
NB7L572 incorporates a pair of Select pins that will choose one of
four differential inputs and will produce two identical LVPECL output
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, NB7L572 is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The NB7L572 INx/INx inputs, outputs and core logic are powered
by a 2.5 V $5% V or 3.3 V $10% power supply. The two differential
LVPECL outputs will swing 750 mV when externally terminated with
a 50 W resistor to V_CC – 2 V, and are optimized for low skew and
minimal jitter.
The NB7L572 is offered in a low profile 5x5 mm 32-pin QFN
Pb-free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB7L572 is a member of the GigaComm™ family of high
performance clock products.
Features
• Input Data Rate > 10.7 Gb/s Typical
• Data Dependent Jitter < 15 ps
• Maximum Input Clock Frequency > 7 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:2 LVPECL Outputs, < 15 ps max
• 4:1 Multi−Level Mux Inputs, Accepts LVPECL, CML LVDS
• 150 ps Typical Propagation Delay
• 45 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 750 mV Peak-to-Peak, Typical
• Operating Range: V_CC = 2.375 V to 3.6 V
• Internal 50 W Input Termination Resistors
• V_REFAC Reference Output
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING
DIAGRAM*
32
1
NB7L
572
AWLYYWWG
A
= Assembly Site
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
IN0
50W
V_T0
50W
IN0
V_REFAC0
IN1
0
50W
V_T1
50W
Q0
IN1
1
Q0
V_REFAC1
IN2
2
50W
Q1
V_T2
Q1
50W
IN2
V_REFAC2
3
IN3
50W
V_T3
50W
IN3
V_REFAC3
SEL0
SEL1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
1
December, 2008 − Rev. 1
Publication Order Number:
NB7L572/D