NB7L32M Datasheet, PDF (1/11 Pages) ON Semiconductor – 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination

NB7L32M
2.5V/3.3V, 14GHz ÷2 Clock
Divider w/CML Output and
Internal Termination
Descriptions
The NB7L32M is an integrated ÷2 divider with differential clock
inputs and asynchronous reset.
Differential clock inputs incorporate internal 50 W termination
resistors and accept LVPECL (Positive ECL), CML, or LVDS. The
high frequency reset pin is asserted on the rising edge. Upon
power−up, the internal flip−flops will attain a random state; the reset
allows for the synchronization of multiple NB7L32M’s in a system.
The differential 16 mA CML output provides matching internal
50 W termination which guarantees 400 mV output swing when
externally receiver terminated 50 W to V_CC (See Figure 16).
The device is housed in a small 3x3 mm 16 pin QFN package.
Features
• Maximum Input Clock Frequency 14 GHz Typical
• 200 ps Max Propagation Delay
• 30 ps Typical Rise and Fall Times
• < 0.5 ps Maximum (RMS) Random Clock Jitter
• Operating Range: V_CC = 2.375 V to 3.465 V with V_EE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output), Differential
Output Only
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• These are Pb−Free Devices
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
32M
ALYWG
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
FUNCTIONAL BLOCK DIAGRAM
R
V_CC
VTCLK
CLK
50 W
CLK
VTCLK
50 W
R1
V_EE
Reset
Q
Divide by 2
Q
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 0
TRUTH TABLE
CLK
CLK
R
Q
Q
x
x
H
L
H
Z
W
L
÷2
÷2
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
1
Publication Order Number:
NB7L32M/D