NB7L111M Datasheet, PDF (1/13 Pages) ON Semiconductor – 2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output

NB7L111M
2.5V / 3.3V, 6.125Gb/s 1:10
Differential Clock/Data
Driver with CML Output
Description
The NB7L111M is a low skew 1–to–10 differential clock/data
driver, designed with clock/data distribution in mind. It accepts two
clock/data sources into multiplexer input and reproduces ten identical
CML differential outputs. This device is ideal for clock/data
distribution across the backplane or a board, and redundant clock
switchover applications.
The input signals can be either differential or single–ended (if the
external reference voltage is provided). Differential inputs incorporate
internal 50 W termination resistors and accept Negative ECL (NECL),
Positive ECL (PECL), LVCMOS, LVTTL, CML, or LVDS (using
appropriate power supplies). The differential 16 mA CML output
provides matching internal 50 W termination, and 400 mV output
swing when externally terminated 50 W to V_CC.
The NB7L111M operates from a 2.5 V $5% supply or a
3.3 V $5% supply and is guaranteed over the full industrial
temperature range of −40°C to +85°C. This device is packaged in a
low profile 8x8 mm, QFN−52 package with 0.5 mm pitch (see
package dimension on the back of the datasheet).
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
• Maximum Input Clock Frequency > 5.5 GHz Typical
• Maximum Input Data Rate > 6.125 Gb/s Typical
• < 0.5 ps Maximum Clock RMS Jitter
• < 15 ps Maximum Data Dependent Jitter at 3.125 Gb/s
• 50 ps Typical Rise and Fall Times
• 240 ps Typical Propagation Delay
• 2 ps Typical Duty Cycle Skew
• 10 ps Typical Within Device Skew
• 15 ps Typical Device−to−Device Skew
• Operating Range: V_CC = 2.5 V $5 and 3.3 V $5
• 400 mV Differential CML Output Swing
• 50 W Internal Input and Output Termination Resistors
• Pb−Free Packages are Available*
http://onsemi.com
1 52
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB7L
111M
AWLYYWWG
A
= Assembly Site
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
January, 2006 − Rev. 1
Publication Order Number:
NB7L111M/D