NB6N239S_13 Datasheet, PDF (1/12 Pages) ON Semiconductor – 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT Clock Divider

NB6N239S
3.3 V, 3.0 GHz Any
Differential Clock IN to
LVDS OUT ÷1/2/4/8, ÷2/4/8/16
Clock Divider
Description
The NB6N239S is a high−speed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios; B1/2/4/8
and B2/4/8/16. Both divider circuits drive LVDS compatible outputs.
(More device information on page 7). The NB6N239S is a member
of the ECLinPS MAX™ family of high performance clock products.
Features
• Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with B1)
• Input Compatibility with LVDS/LVPECL/CML/HSTL/HCSL
• Rise/Fall Time 120 ps Typical
• < 5 ps Typical Within Device Output Skew
• Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
• Internal 50 W Termination Provided
• Random Clock Jitter < 2 ps RMS
• QA B1 Edge Aligned to QB Bn Edge
• Operating Range: V_CC = 3.0 V to 3.465 V with GND = 0 V
• Master Reset for Synchronization of Multiple Chips
• V_BBAC Reference Output
• Synchronous Output Enable/Disable
• TIA/EIA − 644 Compliant
• These Devices are Pb−Free and are RoHS Compliant
SELA0
SELA1
CLK
VT
CLK
50 W
50 W
V_BBAC
EN
SELB0
SELB1
+
MR
B1
B2
A _B4
B8
R
B2
B4
B _B8
B16
Figure 1. Simplified Logic Diagram
http://onsemi.com
1
Bottom View
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB6N
239S
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
QA
QA
QB
QB
© Semiconductor Components Industries, LLC, 2013
1
January, 2013 − Rev. 6
Publication Order Number:
NB6N239S/D