NB6LQ572M Datasheet, PDF (1/10 Pages) ON Semiconductor – 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator

NB6LQ572M
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 CML Clock/Data Fanout
/ Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB6LQ572M is a high performance differential 4:1 Clock /
Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that
operates up to 6 GHz / 8 Gbps respectively with a 2.5 V or 3.3 V
power supply.
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Clock / Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB6L572M, which is pin−compatible to the
NB6LQ572M.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6LQ572M incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
CML output copies of Clock or Data.
As such, the NB6LQ572M is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The two differential CML outputs will swing 400 mV when
externally loaded and terminated with a 50 W resistor to V_CC and are
optimized for low skew and minimal jitter.
The NB6LQ572M is offered in a low profile 5x5mm 32−pin QFN
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com. The NB6LQ572M
is a member of the ECLinPS MAX™ family of high performance
clock products.
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB6L
Q572M
AWLYYWWG
G
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Features
• Input Data Rate > 8 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 6 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:2 CML Outputs, < 15 ps max
• 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML
LVDS
• Input EQ for Backplane and Cable Interconnect
Compensation
• 150 ps Typical Propagation Delay
• 45 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak,
Typical
• Operating Range: V_CC = 2.375 V to 3.6 V with
GND = 0 V
• Internal 50 W Input Termination Resistors
• V_REFAC Reference Output
• QFN−32 Package, 5mm x 5mm
• 40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2009
1
November, 2009 − Rev. 0
Publication Order Number:
NB6LQ572M/D