NB6L295MNGEVB Datasheet, PDF (1/13 Pages) ON Semiconductor – 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs

NB6L295
2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential
LVPECL Outputs
Multi−Level Inputs w/ Internal Termination
The NB6L295 is a Dual Channel Programmable Delay Chip
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designed primarily for Clock or Data de−skewing and timing
adjustment. The NB6L295 is versatile in that two individual variable
delay channels, PD0 and PD1, can be configured in one of two
operating modes, a Dual Delay or an Extended Delay.
MARKING
DIAGRAM*
24
In the Dual Delay Mode, each channel has a programmable delay
section which is designed using a matrix of gates and a chain of
multiplexers. There is a fixed minimum delay of 3.2 ns per channel.
The Extended Delay Mode amounts to the additive delay of PD0
plus PD1 and is accomplished with the Serial Data Interface MSEL bit
set High. This will internally cascade the output of PD0 into the input
of PD1. Therefore, the Extended Delay path starts at the IN0/IN0
24 1
A
L
Y
W
QFN−24
1
MN SUFFIX
CASE 485L
= Assembly Location
= Wafer Lot
= Year
= Work Week
NB6L
295
ALYWG
G
inputs, flows through PD0, cascades to the PD1 and outputs through
Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended
G
= Pb−Free Package
(Note: Microdot may be in either location)
Delay Mode.
The required delay is accomplished by programming each delay
*For additional marking information, refer to
Application Note AND8002/D.
channel via a 3−pin Serial Data Interface, described in the application
ORDERING INFORMATION
section. The digitally selectable delay has an increment resolution of
typically 11 ps with a net programmable delay range of either 0 ns to
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the
Extended Delay Mode.
The Multi−Level Inputs can be driven directly by differential
LVPECL, LVDS or CML logic levels; or by single ended LVPECL,
LVCMOS or LVTTL. A single enable pin is available to control both
inputs. The SDI input pins are controlled by LVCMOS or LVTTL
level signals. The NB6L295 LVPECL output contains temperature
compensation circuitry. This device is offered in a 4 mm x 4 mm
24−pin QFN Pb−free package. The NB6L295 is a member of the
ECLinPS MAX™ family of high performance products.
Features
• Input Clock Frequency > 1.5 GHz with 550 mV
V_OUTPP
• Input Data Rate > 2.5 Gb/s
• Programmable Delay Range: 0 ns to 6 ns per Delay
Channel
• Programmable Delay Range: 0 ns to 11.2 ns for
Extended Delay Mode
• Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel
• Total Delay Range: 6 ns to 17 ns in Extended Delay
Mode
• Monotonic Delay: 11 ps Increments in 511 Steps
• Linearity $20 ps, Maximum
• 100 ps Typical Rise and Fall Times
• 3 ps Typical Clock Jitter, RMS
• 20 ps Pk−Pk Typical Data Dependent Jitter
• LVPECL, CML or LVDS Differential Input Compatible
• LVPECL, LVCMOS, LVTTL Single−Ended Input
Compatible
• 3−Wire Serial Interface
• Input Enable/Disable
• Operating Range: V_CC = 2.375 V to 3.6 V
• LVPECL Output Level; 780 mV Peak−to−Peak, Typical
• Internal 50 W Input Termination Provided
• −40°C to 85°C Ambient Operating Temperature
• 24−Pin QFN, 4 mm x 4 mm
• These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2012
1
March, 2012 − Rev. 4
Publication Order Number:
NB6L295/D