NB6L239 Datasheet, PDF (1/12 Pages) ON Semiconductor – 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider

NB6L239
2.5 V / 3.3 V Any Differential
Clock IN to Differential
LVPECL OUT ÷1/2/4/8,
÷2/4/8/16 Clock Divider
Features
The NB6L239 is a high−speed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios; B1/2/4/8
and B2/4/8/16. Both divider circuits drive a pair of differential
LVPECL outputs. (More device information on page 7).
• Maximum Clock Input Frequency, 3.0 GHz
• Input Compatibility with LVDS/LVPECL/CML/HSTL
• Rise/Fall Time 70 ps Typical
• < 10 ps Typical Output−to−Output Skew
• Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs
• Internal 50 W Termination Provided
• Random Clock Jitter < 1 ps RMS
• Divide−by−1 Edge of QA Aligned to QB Divided Output
• Operating Range: V_CC = 2.375 V to 3.465 V with V_EE = 0 V
• Master Reset for Synchronization of Multiple Chips
• V_BBAC Reference Output
• Synchronous Output Enable/Disable
http://onsemi.com
MARKING DIAGRAM*
Bottom View
QFN−16
MN SUFFIX
CASE 485G
XXXX
XXXX
ALYW
XXXX
A
L
Y
W
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
SELA0
SELA1
CLK
VT
CLK
EN
SELB0
SELB1
+
MR
QA
QA
QB
QB
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2004
1
April, 2004 − Rev. 0
Publication Order Number:
NB6L239/D