NB6L14_07 Datasheet, PDF (1/10 Pages) ON Semiconductor – 2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

NB6L14
2.5 V/3.3 V 3.0 GHz
Differential 1:4 LVPECL
Fanout Buffer
Multi- Level Inputs with Internal Termination
Description
The NB6L14 is a 3.0 GHz differential 1:4 LVPECL clock or data
fanout buffer. The differential inputs incorporate internal 50 W
termination resistors that are accessed through the VT pin. This feature
allows the NB6L14 to accept various logic standards, such as
LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The
VREF_AC reference output can be used to rebias capacitor-coupled
differential or single-ended input signals. The 1:4 fanout design was
optimized for low output skew applications.
The NB6L14 is a member of the ECLinPS MAX™ family of high
performance clock and data management products.
Features
•ăInput Clock Frequency > 3.0 GHz
•ăInput Data Rate > 2.5 Gb/s
•ă< 20 ps Within Device Output Skew
•ă350 ps Typical Propagation Delay
•ă150 ps Typical Rise and Fall Times
•ăDifferential LVPECL Outputs, 700 mV Amplitude, Typical
•ăLVPECL Mode Operating Range: V_CC = 2.375 V to 3.63 V with
GND = 0 V
•ăInternal 50 W Input Termination Resistors Provided
•ăVREF_AC Reference Output Voltage
•ă-40 °C to +85°C Ambient Operating Temperature
•ăAvailable in 3 mm x 3 mm 16 Pin QFN
•ăThese are Pb-Free Devices
http://onsemi.com
QFN-16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
14
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
Q1
IN
Q1
VT
IN
Q2
Q2
EN
DQ
Q3
Q3
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©Ă Semiconductor Components Industries, LLC, 2007
1
May, 2007 - Rev. 1
Publication Order Number:
NB6L14/D