NB6L11_06 Datasheet, PDF (1/12 Pages) ON Semiconductor – 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator

NB6L11
2.5 V/3.3 V Multilevel Input to
Differential LVPECL/LVNECL
1:2 Clock or Data
Fanout Buffer/Translator
The NB6L11 is an enhanced differential 1:2 clock or data fanout
buffer/translator. The device has the same pinout and is functionally
equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW
jitter and LOW power consumption.
Differential input can be configured to accept single−ended signal
by applying an external reference voltage to unused complementary
input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS,
CML, or LVDS. The outputs are 800 mV ECL signals.
Features
• Maximum Input Clock Frequency w 6 GHz Typical
• Maximum Input Data Rate w 6 Gb/s Typical
• Low 14 mA Typical Power Supply Current
• 150 ps Typical Propagation Delay
• 5 ps Typical Within Device Skew
• 75 ps Typical Rise/Fall Times
• PECL Mode Operating Range:
V_CC = 2.375 V to 3.465 V with V_EE = 0 V
• NECL Mode Op rating Range:
V_CC = 0 V with V_EE = −2.375 V to −3.465 V
• Open Input Default State
• Q Outputs Will Default LOW with Inputs Open or at V_EE
• LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input
Compatible
• Pb−Free Packages are Available
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SO−8
D SUFFIX
CASE 751
8
6L11
ALYW G
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
6L11
ALYW G
G
1
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 6
Publication Order Number:
NB6L11/D