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NB4N855S_06 Datasheet, PDF (1/9 Pages) ON Semiconductor – 3.3 V, 1.5 Gb/s Dual AnyLevel TM to LVDS Receiver/Driver/Buffer/ Translator | |||
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NB4N855S
3.3 V, 1.5 Gb/s Dual
AnyLevel⢠to LVDS
Receiver/Driver/Buffer/
Translator
Description
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel input signal (LVPECL, CML, HSTL,
LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance,
noise immunity of the system design, and transmission line media, this
device will receive, drive or translate data or clock signals up to
1.5 Gb/s or 1.0 GHz, respectively. This device is pinâforâpin plug in
compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of
GND + 50 mV to VCC â 50 mV. This feature is ideal for translating
differential or singleâended data or clock signals to 350 mV typical
LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S
is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
⢠Guaranteed Input Clock Frequency up to 1.0 GHz
⢠Guaranteed Input Data Rate up to 1.5 Gb/s
⢠490 ps Maximum Propagation Delay
⢠1.0 ps Maximum RMS Jitter
⢠180 ps Maximum Rise/Fall Times
⢠Single Power Supply; VCC = 3.3 V ±10%
⢠Temperature Compensated TIA/EIAâ644 Compliant LVDS Outputs
⢠GND + 50 mV to VCC â 50 mV VCMR Range
⢠PbâFree Package is Available
http://onsemi.com
1
Microâ10
M SUFFIX
CASE 846B
MARKING
DIAGRAM*
10
855S
AYWG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
G
= PbâFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
D0
Q0
D0
Q0
D1
Q1
D1
Q1
Functional Block Diagram
Device DDJ = 7 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
TIME (133 ps/div)
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5
(VINPP = 100 mV, Input Signal DDJ = 24 ps)
© Semiconductor Components Industries, LLC, 2006
1
April, 2006 â Rev. 2
Publication Order Number:
NB4N855S/D
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