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NB4N840M Datasheet, PDF (1/9 Pages) ON Semiconductor – 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination | |||
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NB4N840M
3.3V 3.2Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination
Description
The NB4N840M is a highâbandwidth fully differential dual
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET, DWDM, Gigabit Ethernet and
high speed switching. Fully differential design techniques are used to
minimize jitter accumulation, crosstalk, and signal skew, which make
this device ideal for loopâthrough and protection channel switching
applications.
Internally terminated differential CML inputs accept ACâcoupled
LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50 W input and output termination resistor, the need for
external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50 W terminations, and 400 mV output swings when
externally terminated, 50 W to VCC.
Singleâended LVCMOS/LVTTL SEL inputs control the routing of
the signals through the crosspoint switch which makes this device
configurable as 1:2 fanâout, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32âpin QFN package.
Features
⢠Plugâin compatible to the MAX3840 and SY55859L
⢠Maximum Input Clock Frequency 2.7 GHz
⢠Maximum Input Data Frequency 3.2 Gb/s
⢠225 ps Typical Propagation Delay
⢠80 ps Typical Rise and Fall Times
⢠7 ps Channel to Channel Skew
⢠430 mW Power Consumption
⢠< 0.5 ps RMS Jitter
⢠7 ps PeakâtoâPeak Data Dependent Jitter
⢠Power Saving Feature with Disabled Outputs
⢠Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
⢠CML Output Level (400 mV PeakâtoâPeak Output), Differential
Output
⢠These are PbâFree Devices
http://onsemi.com
MARKING
DIAGRAM
1
1 32
QFN32
MN SUFFIX
CASE 488AM
A
WL
YY
WW
G
NB4N
840M
ALYWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbâFree Package
DA0
DA0
CML
DA1
DA1
CML
0
CML
1
0
CML
1
QA0
QA0
ENA0
SELA0
QA1
QA1
ENA1
SELA1
DB0
CML
DB0
0
CML
1
QB0
QB0
ENB0
SELB0
DB1
DB1
CML
0
CML
1
QB1
QB1
ENB1
SELB1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
August, 2006 â Rev. 2
Publication Order Number:
NB4N840M/D
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