NB4N527S Datasheet, PDF (1/10 Pages) ON Semiconductor – 3.3V, 2.5Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination

NB4N527S
3.3V, 2.5Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator with Internal
Input Termination
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel^TM input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
The NB4N527S has a wide input common mode range of
GND + 50 mV to V_CC − 50 mV combined with two 50 W internal
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
The device is offered in a small 3 mm x 3 mm QFN−16 package.
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
• Maximum Input Clock Frequency up to 1.5 GHz
• Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
• 470 ps Maximum Propagation Delay\
• 1 ps Maximum RMS Jitter
• 140 ps Maximum Rise/Fall Times
• Single Power Supply; V_CC = 3.3 V $10%
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
• Internal 50 W Termination Resistor per Input Pin
• GND + 50 mV to V_CC − 50 mV V_CMR Range
• Pb−Free Packages are Available
Device DDJ = 10 ps
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB4N
527S
ALYW G
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
50 W*
VTD0
D0
Q0
D0
Q0
50 W*
VTD0
VTD1
50 W*
D1
Q1
D1
Q1
50 W*
VTD1
Figure 1. Functional Block Diagram
*R_TIN
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2^23−1 (V_INPP = 400 mV; Input Signal DDJ = 14 ps)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 3
Publication Order Number:
NB4N527S/D