NB4N121K Datasheet, PDF (1/10 Pages) ON Semiconductor – 3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output

NB4N121K
3.3V Differential In 1:21
Differential Fanout Clock
Driver with HCSL level
Output
Description
The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Single-ended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper V_REFAC supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors.
Output drive current at I_REF (Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect I_REF to V_CC. See
Figure 9.
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K's performance to distribute low skew
clocks across the backplane or the motherboard.
Features
•ăTypical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
•ă340 ps Typical Rise and Fall Times
•ă800 ps Typical Propagation Delay
•ăDtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
•ă<1 ps RMS Additive Clock jitter
•ăOperating Range: V_CC = 3.0 V to 3.6 V with V_EE = 0 V
•ăDifferential HCSL Output Level (700 mV Peak-to-Peak)
•ăPb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
1 52
QFN-52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB4N
121K
AWLYYWWG
A
= Assembly Site
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK
CLK
CLK
VTCLK
V_CC
GND
Q0
Q0
Q1
Q1
R_REF
Q19
Q19
Q20
I_REF ^Q20
Figure 1. Pin Configuration (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©Ă Semiconductor Components Industries, LLC, 2007
1
June, 2007 - Rev. 0
Publication Order Number:
NB4N121K/D