NB4L52_09 Datasheet, PDF (1/8 Pages) ON Semiconductor – 2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop

NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip-Flop
with Reset
Multi−Level Inputs to LVPECL Translator
w/ Internal Termination
The NB4L52 is a differential Data and Clock D flip−flop with a
differential asynchronous Reset. The differential inputs incorporate
internal 50 W termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
• Maximum Input Clock Frequency > 4 GHz Typical
• 330 ps Typical Propagation Delay
• 145 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
• Operating Range: V_CC = 2.375 V to 5.5 V with V_EE = 0 V
• Internal Input Termination Resistors, 50 W
• Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
LVEP, EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB4L
52
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
Data
D
Q
VTD
VTCLK
Q
CLK
CLK
VTCLK
Clock
Reset
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 3
VTR R R VTR
Figure 1. Logic Diagram
Table 1. TRUTH TABLE
R
D
CLK
Q
H
x
x
L
L
L
Z
L
L
H
Z
H
Z = LOW to HIGH Transition
x = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1
Publication Order Number:
NB4L52/D