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NB3W800L_16 Datasheet, PDF (1/17 Pages) ON Semiconductor – Differential 1:8 HCSLCompatible Push-Pull Clock
NB3W800L
3.3 V 100/133 MHz
Differential 1:8 HCSL-
Compatible Push-Pull Clock
ZDB/Fanout Buffer for PCIe)
Description
The NB3W800L is a low−power 8−output differential buffer that
meets all the performance requirements of the DB800ZL
specification. The NB3W800L is capable of distributing the reference
clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe
Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect
(Intel SMI) applications. A fixed, internal feedback path maintains low
drift for critical QPI applications.
Features
• 8 Differential Clock Output Pairs @ 0.7 V
• Low−power NMOS Push−pull HCSL Compatible Outputs
• Cycle−to−cycle Jitter <50 ps
• Output−to−output Skew <50 ps
• Input−to−output Delay Variation <100 ps
• PCIe Gen3 Phase Jitter <1.0 ps RMS
• QPI 9.6GT/s 12UI Phase Jitter <0.2 ps RMS
• Pseudo−External Fixed Feedback for Lowest Input−to−output Delay
• Individual OE Control; Hardware Control of Each Output
• PLL Configurable for PLL Mode or Bypass Mode (Fanout
Operation)
• 100 MHz or 133 MHz PLL Mode Operation; Supports PCIe and QPI
Applications
• Selectable PLL Bandwidth; Minimizes Jitter Peaking in Downstream
PLL’s
• SMBus Programmable Configurations
• Spread Spectrum Compatible; Tracks Input Clock Spreading for Low
EMI
• These are Pb−Free Devices
www.onsemi.com
1 48
CASE 485DP
MARKING
DIAGRAM
1
NB3W800L
AWLYYWWG
NB3W800L = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NB3W800LMNG
QFN48
(Pb−Free)
490 / Tray
NB3W800LMNTXG QFN48 2500 / Tape &
(Pb−Free)
Reel
NB3W800LMNTWG QFN48 2500 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 2
Publication Order Number:
NB3W800L/D