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NB3W1900L Datasheet, PDF (1/18 Pages) ON Semiconductor – 3.3 V 100/133 MHz Differential 1:19 HCSL-Compatible Push‐Pull | |||
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NB3W1900L
3.3 V 100/133 MHz
Differential 1:19
HCSL-Compatible PushâPull
Clock ZDB/Fanout Buffer for
PCIe[
http://onsemi.com
Description
The NB3W1900L differential clock buffers are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point-to-point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI), PCIe Gen1/Gen2/Gen3.The NB3W1900L internal PLL is
optimized to support 100âMHz and 133 MHz frequency operation.
The NB3W1900L is developed with the low-power NMOS Push-Pull
buffer type.
Features
⢠19 Low Power Differential Clock Output Pairs @ 0.7 V
⢠Output-to-Output Skew Performance: < 85 ps
⢠Cycle-to-Cycle Jitter (PLL Mode): < 50ps
⢠Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter
Compliant)
⢠Input-to-Output Delay Variation: < 50 ps
⢠Fixed-Feedback for Lowest Input-to-Output Delay Variation
⢠Spread Spectrum Compatible; Tracks Input Clock Spreading for Low
EMI
⢠100 MHz and 133 MHz PLL Mode to Meet the Next Generation
PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter
⢠Individual OE Control via SMBus
⢠Low-Power NMOS Push-Pull HCSLâCompatible Outputs
⢠PLL Configurable for PLL Mode or Bypass Mode
(Fanout Operation)
⢠SMBus Address Configurable to Allow Multiple Buffers in a Single
Control Network
⢠Programmable PLL Bandwidth
⢠Two Tri-level Addresses Selection (Nine SMBus Addresses)
⢠QFN 72-pin Package, 10 mm à 10 mm
⢠These are Pb-Free Devices
1 72
QFN72
MN SUFFIX
CASE 485DK
MARKING DIAGRAM
1
NB3W
1900L
AWLYYWWG
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
October, 2014 â Rev. 0
Publication Order Number:
NB3W1900L/D
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