NB3V8312C Datasheet, PDF (1/11 Pages) ON Semiconductor – Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer

NB3V8312C
Ultra-Low Jitter, Low Skew
1:12 LVCMOS/LVTTL Fanout
Buffer
The NB3V8312C is a high performance, low skew LVCMOS
fanout buffer which can distribute 12 ultra−low jitter clocks from an
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LVCMOS/LVTTL input up to 250 MHz.
The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tri−stated) via the OE input, or enabled when High.
The NB3V8312C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW, potential output glitching or
runt pulse generation is eliminated.
LQFP−32
FA SUFFIX
CASE 873A
1 32
QFN32
MN SUFFIX
CASE 488AM
Separate V_DD core and V_DDO output supplies allow the output
V_DDO
buffers to operate at the same supply as the V_DD (V_DD = V_DDO) or
V_DD
from a lower supply voltage. Compared to single−supply operation,
GND
Q0
dual supply operation enables lower power consumption and
Q1
output−level compatibility.
R_PU
The V_DD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V,
CLK_EN
D
Q
Q2
while the V_DDO output supply voltage can be set to 3.3 V, 2.5 V, or
Q3
1.8 V, with the constraint that V_DD ≥ V_DDO.
This buffer is ideally suited for various networking, telecom, server
Q4
and storage area networking, RRU LO reference distribution, medical
Q5
and test equipment applications.
CLK
Q6
R_PD
Features
Q7
• Power Supply Modes:
V_DD (Core) / V_DDO (Outputs)
Q8
3.3 V
/ 3.3 V
Q9
3.3 V
/ 2.5 V
3.3 V
/ 1.8 V
Q10
2.5 V
2.5 V
1.8 V
/ 2.5 V
/ 1.8 V
/ 1.8 V
Q11
R_PU
OE
• 250 MHz Maximum Clock Frequency
Figure 1. Simplified Logic Diagram
• Accepts LVCMOS, LVTTL Clock Inputs
• LVCMOS Compatible Control Inputs
ORDERING AND MARKING INFORMATION
• 12 LVCMOS Clock Outputs
• Synchronous Clock Enable
See detailed ordering and shipping information on page 9 of
this data sheet.
• Output Enable to High Z State Control
• 150 ps Max. Skew Between Outputs
• Temp. Range −40°C to +85°C
• 32−pin LQFP and QFN Packages
Applications
• Networking
• Telecom
• Storage Area Network
• These are Pb−Free Devices
End Products
• Servers
• Routers
• Switches
© Semiconductor Components Industries, LLC, 2013
1
August, 2013 − Rev. 0
Publication Order Number:
NB3V8312C/D