NB3N65027 Datasheet, PDF (1/7 Pages) ON Semiconductor – 3.3V Programmable 3-PLL Clock Synthesizer

NB3N65027
3.3V Programmable 3-PLL Clock
Synthesizer with
6 LVTTL/LVCMOS Outputs w/OE
The NB3N65027 is a LVCMOS PLL−synthesized clock generator.
It accepts a 10 MHz to 27 MHz clock or fundamental mode crystal as
the reference source and drives three independent, low noise
phase−locked loops (PLLs).
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Control lines ACSx, BCSx and CCS will select their appropriate
bank output frequencies. ACS1 and BCS1 are two−level
MARKING DIAGRAM
LVTTL/LVCMOS inputs, High and Low. ACS0, BCS0 and CCS are
three−level LVCMOS inputs, High, Mid and Low.
The NB3N65027 has three independent LVTTL/LVCMOS output
3N65027
AWLYWWG
banks of two outputs each. Banks A and B offer a 1X and a 1/2X
output. Using a 25 MHz crystal, the selectable output frequencies
range from 16 2/3 MHz to 133 1/3 MHz. A 12.5 MHz crystal offers
QSOP20
CASE 492AC
from 8 1/3 MHz to 66 2/3 MHz. In addition, the NB3N65027 will
generate a buffered reference LVTTL/LVCMOS output, REFOUT,
10 MHz to 27 MHz. See Tables 2 through 9 for the variety of available
output frequencies. The OE pin, when set LOW, will disable the output
drivers to high impedance.
The NB3N65027 operates from a single +3.3 V supply across the
3N65027 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
operating temperature range from −40°C to +85°C, and is offered in a
QSOP−20 RoHS compliant package.
The NB3N65027 provides the optimum combination of low cost,
flexibility, and high performance for Network, PCI and SDRAM
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
applications.
Features
• 12.5 MHz or 25 MHz Fundamental Crystal or Clock
Input
• Six Output Clocks with Selectable Frequencies
• Buffered Crystal Reference Output
• SDRAM Frequencies of 67, 83, 100, and 133 MHz
• Operating Range: V_CC = 3.3 V ±10%
• QSOP−20 Package, 150 mil
• −40°C to +85°C Ambient Operating Temperature
• These Devices are Pb−Free and are RoHS Compliant
• LVCMOS with 25 mA Output Drive Capability at TTL
Levels
VDD
ACS1
ACS0
BCS1
BCS0
CCS
25 or 12.5 MHz
crystal or clock
X1/ICLK
X2 C_LX2
PLLA
PLLB
PLLC
Buffer /
Oscillator
Clock
Synthesis
and Control
Circuitry
C_LX1
GND
Figure 1. Simplified Logic Diagram
CLKA1
B2
CLKA2
CLKB1
B2
CLKB2
CLKC1
CLKC2
REFOUT
OE (all outputs)
© Semiconductor Components Industries, LLC, 2011
1
June, 2011 − Rev. 2
Publication Order Number:
NB3N65027/D