NB3N51032_16 Datasheet, PDF (1/13 Pages) ON Semiconductor – Dual HCSL/LVDS Clock Generator

NB3N51032
3.3 V, Crystal to 25 MHz,
100 MHz, 125 MHz and
200 MHz Dual HCSL/LVDS
Clock Generator
The NB3N51032 is a precision, low phase noise clock generator that
supports PCI Express and Ethernet requirements. The device accepts a
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25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 10). The NB3N51032 provides selectable
spread options of −0.5% and −0.75% for applications demanding low
Electromagnetic Interference (EMI) as well as optimum performance
with no spread option.
Features
• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
MARKING
DIAGRAM
16
16
NB3N
1
TSSOP−16
DT SUFFIX
1032
ALYWG
1
G
CASE 948F
A
= Assembly Location
L
= Wafer Lot
• External Loop Filter is Not Required
• HCSL Differential Output or LVDS with Proper Termination
• Four Selectable Multipliers of the Input Frequency
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
• Output Enable with Tri−State Outputs
• PCIe Gen 1, Gen 2, Gen 3 Compliant
• Spread of −0.5%, −0.75% and No Spread
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
• Phase Noise: @ 100 MHz
Offset Noise Power
Applications
• Networking
100 Hz −88 dBc/Hz
• Consumer
1 kHz −118 dBc/Hz
10 kHz −131 dBc/Hz
100 kHz −132 dBc/Hz
1 MHz −144 dBc/Hz
10 MHz −155 dBc/Hz
• Typical Period Jitter RMS of 1.5 ps
• Computing and Peripherals
• Industrial Equipment
• PCIe Clock Generation Gen 1, Gen 2 and Gen 3
• Gigabit Ethernet
• FB DIMM
• Operating Supply Voltage Range 3.3 V ±5%
• Industrial Temperature Range −40°C to +85°C
• Functionally Compatible with IDT557−03,
IDT5V41065, IDT5V41235 with enhanced performance
• These are Pb−Free Devices
End Products
• Switch and Router
• Set Top Box, LCD TV
• Servers, Desktop Computers
• Automated Test Equipment
V_DD
SS0 SS1
X1/CLK
Spread Spectrum
Circuit
25 MHz Clock or
Crystal X2
Clock Buffer
Crystal Oscillator
Phase
Detector
Charge
Pump
BN
VCO
HCSL
Output
HCSL
Output
CLK0
CLK0
CLK1
CLK1
V_DD = VDDODA = VDDXD
GND = GNDODA = GNDXD
GND
S0
S1
Figure 1. NB3N51032 Simplified Logic Diagram
OE IREF
© Semiconductor Components Industries, LLC, 2016
1
April, 2016 − Rev. 2
Publication Order Number:
NB3N51032/D