NB3N3020DTGEVB Datasheet, PDF (1/9 Pages) ON Semiconductor – 3.3 V, LVPECL/LVCMOS Clock Multiplier

NB3N3020
3.3 V, LVPECL/LVCMOS
Clock Multiplier
Description
The NB3N3020 is a high precision, low phase noise selectable clock
multiplier. The device takes a 5 – 27 MHz fundamental mode parallel
resonant crystal or a 2 − 210 MHz LVCMOS single ended clock source
and generates a differential LVPECL output and a single ended
LVCMOS/LVTTL output at a selectable clock output frequency which
is a multiple of the input clock frequency. Three tri−level (Low, Mid,
High) LVCMOS/LVTTL single ended select pins set one of 26
possible clock multipliers. The LVCMOS/LVTTL output enable
(OE1) tri−states the LVCMOS/LVTTL clock output (CLK1) when
low. When the LVTTL/LVCMOS output enable (OE2) is LOW,
LVPECL CLK2 is forced LOW and LVPECL CLK2 is forced HIGH.
This device is housed in 5 mm x 4.4 mm narrow body TSSOP 16 pin
package.
Features
• Selectable Clock Multiplier
• External Loop Filter is Not Required
• LVPECL Differential Output
• LVCMOS/ LVTTL Outputs
• RMS Period Jitter of 5 ps
• Jitter or Low Phase Noise at 125 MHz [25 MHz Input]:
Offset
Noise Power
100 Hz
−95 dBc/Hz
1 kHz
−107 dBc/Hz
10 kHz
−112 dBc/Hz
100 kHz
−117 dBc/Hz
1 MHz
−117 dBc/Hz
10 MHz
−134 dBc/Hz
• Operating Range 3.3 V ±10%
• Industrial Temperature Range −40°C to +85°C
• These are Pb−Free Devices
http://onsemi.com
16
1
TSSOP−16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
16
NB3N
3020
ALYWG
1
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(*Note: Microdot may be in either location)
VDD
X1/CLK
X2
Sel2
Sel1
Sel0
OE1
GND
PIN CONFIGURATION
1
16
(Top View)
OE2
VDD
CLK2
CLK2
GND
VDD
CLK1
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
January, 2014 − Rev. 4
Publication Order Number:
NB3N3020/D