NB3N3002 Datasheet, PDF (1/7 Pages) ON Semiconductor – 3.3V, Crystal-to-HCSL Clock Generator

NB3N3002
3.3V, Crystal-to-HCSL
Clock Generator
Description
The NB3N3002 is a high precision, low phase noise clock generator
that supports PCI−Express and Ethernet requirements. The device
takes a 25 MHz fundamental mode parallel resonant crystal and
generates differential HCSL output at 25 MHz, 100 MHz, 125 MHz or
200 MHz clock frequencies. Outputs can interface with LVDS with
proper termination (See Figure 5).
This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16
pin package.
Features
• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
• External Loop Filter is Not Required
• HCSL Differential Output or LVDS with Proper Termination
• Typical TIE RMS jitter of 2.5 ps
• Jitter or Low Phase Noise:
Offset Noise Power
100 Hz −103 dBc
1 kHz −118 dBc
10 kHz −122 dBc
100 kHz −130 dBc
1 MHz −132 dBc
10 MHz −149 dBc
• Operating Range 3.3 V ±5%
• Industrial Temperature Range −40°C to +85°C
• These are Pb−Free Devices
http://onsemi.com
16
1
TSSOP−16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
16
NB3N
3002
ALYWG
1
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
VDD
X1/CLK
25 MHz Clock or
Crystal X2
Clock Buffer
Crystal Oscillator
Phase
Detector
BN
Charge
Pump
VCO
CLK
HSCL
Output
CLK
GND
SEL0
Figure 1. NB3N3002 Simplified Logic Diagram
SEL1 OE IREF
© Semiconductor Components Industries, LLC, 2010
1
June, 2010 − Rev. 2
Publication Order Number:
NB3N3002/D