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NB3N2302 Datasheet, PDF (1/7 Pages) ON Semiconductor – Frequency Multiplier | |||
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NB3N2302
3.3V / 5V 5MHz to 133MHz
Frequency Multiplier and
Zero Delay Buffer
Description
The NB3N2302 is a versatile Zero Delay Buffer that operates from
5 MHz to 133 MHz with a 3.3 V or 5 V power supply. It accepts a
reference input and drives a B1 and a B2 clock output. The
NB3N2302 has an onâchip PLL which locks to the input reference
clock presented on the REF_IN pin. The PLL feedback is required to
be driven to the FBIN pin and can be obtained by connecting either the
OUT1 or OUT2 pin to the FBIN pin.
The Function Select inputs control the various multiplier output
frequency combinations as shown in Table 1.
Features
⢠Output Frequency Range: 5 MHz to 133 MHz
⢠Two LVTTL/LVCMOS Outputs
⢠65 ps Typical Jitter OUT2
⢠115 ps Typical Jitter OUT1
⢠25 ps Typical OutputâtoâOutput Skew
⢠Operating Voltage Range: VDD = 3.3 V $5% or 5 V $10%
⢠Clock Multiplication of the Reference Input Frequency, See Table 1
for Options
⢠Packaged in 8âPin SOIC
⢠â40°C to +85°C Ambient Operating Temperature Range
⢠Ideal for PCIâX and Networking Clocks
⢠These are PbâFree Devices
http://onsemi.com
8
1
SOICâ8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
3N2302
ALYWG
G
1
2302
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbâFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
External feedback connection
to OUT1 or OUT2, not both
FS0
FS1
REF_IN
FBIN
Select Input
Decoding
PLL
÷2
OUT1
OUT2
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2011
1
October, 2011 â Rev. 1
Publication Order Number:
NB3N2302/D
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