NB3N1900K Datasheet, PDF (1/20 Pages) ON Semiconductor – Differential 1:19 HCSL Clock ZDB/Fanout Buffer

NB3N1900K
3.3V 100/133 MHz
Differential 1:19 HCSL
Clock ZDB/Fanout Buffer for
PCIe^[
Description
The NB3N1900K differential clock buffers are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel^® QuickPath Interconnect
(Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is
optimized to support 100 MHz and 133 MHz frequency operation.
The NB3N1900K supports HCSL output levels.
Features
• Fixed Feedback Path for Lowest Input−to−Output Delay
• Eight Dedicated OE# Pins for Hardware Control of Outputs
• PLL Bypass Configurable for PLL or Fanout Operation
• Selectable PLL Bandwidth
• Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
• SMBus Programmable Configurations
• 100 MHz and 133 MHz PLL Mode to Meet the Next Generation
PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter
• 2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
• Cycle−to−Cycle Jitter: < 50 ps
• Output−to−Output Skew: < 65 ps
• Input−to−Output Delay: Fixed at 0 ps
• Input−to−Output Delay Variation: < 50 ps
• Phase Jitter: PCIe Gen3 < 1 ps rms
• Phase Jitter: QPI 9.6GB/s < 0.2 ps rms
• QFN 72−pin Package, 10 mm x 10 mm
• These are Pb−Free Devices
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MARKING
DIAGRAM*
1 72
QFN72
MN SUFFIX
CASE 485DK
1
NB3N
1900K
AWLYYWWG
NB3N1900K = Specific Device Code
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
January, 2015 − Rev. 3
Publication Order Number:
NB3N1900K/D