NB3N121K Datasheet, PDF (1/11 Pages) ON Semiconductor – Differential 1:21 Fanout Clock

NB3N121K
3.3V Differential 1:21
Fanout Clock and Data
Driver with HCSL Outputs
Description
The NB3N121K is a differential 1:21 Clock and Data fanout buffer
with High−speed Current Steering Logic (HCSL) outputs optimized
for ultra low propagation delay variation. The NB3N121K is designed
with HCSL PCI Express clock distribution and FBDIMM applications
in mind.
Inputs can directly accept differential LVPECL, HCSL, and LVDS
signals per Figures 7, 8, and 9. Single ended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external V_th
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50 W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to
LVDS receivers when terminated per Figure 11.
The NB3N121K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
• Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
• 340 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• 100 ps Max Within Device Skew
• 150 ps Max Device−to−Device Skew
• Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
• 0.1 ps Typical RMS Additive Phase Jitter
• LVDS Output Levels Optional with Interface Termination
• Operating Range: V_CC = 3.0 V to 3.6 V with GND = 0 V
• Typical HCSL Output Level (700 mV Peak−to−Peak)
• These are Pb−Free Devices
Applications
• Clock Distribution
• PCIe I, II, III
• Networking
• High End Computing
• Routers
End Products
• Servers
• FBDIMM Memory Card
http://onsemi.com
1 52
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB3N
121K
AWLYYWWG
A
= Assembly Site
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTCLK
Q0
Q1
Q1
CLK
CLK
Q19
VTCLK
V_CC
GND
Q19
Q20
IREF
R_REF
Q20
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
March, 2012 − Rev. 1
Publication Order Number:
NB3N121K/D