NB3L83948C Datasheet, PDF (1/7 Pages) ON Semiconductor – 2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX

NB3L83948C
2.5 V / 3.3 V Differential and
LVTTL/LVCMOS 2:1 MUX to
1:12 LVCMOS Fanout
Description
The NB3L83948C is a pure 2.5 V / 3.3 V (V_DD = V_DDO) or mixed
mode 3.3 V Core (V_DD) / 2.5 V Output (V_DDO) clock distribution
buffer with the capability to select either a differential LVPECL /
LVDS / LVHSTL / SSTL / HCSL or single ended LVCMOS / LVTTL
compatible input clock, such as a Primary or a Test Clock. All other
control inputs (CLK_SEL, CLK_EN, and OE) are LVTTL/LVCMOS
level compatible.
The NB3L83948C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW, potential output glitching or
runt pulse generation is eliminated.
The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tri−stated) via the OE input, or enabled when High.
Fit, Form, and Function compatible with ICS83948I−147,
ICS83948I−01, CY29948AXI, and MPC9448/9448L
Features
• 2.5 V / 3.3V (V_DD = V_DDO) or
3.3 V V_DD / 2.5 V V_DDO Operation:
2.5 $5%, 2.375 to 2.625 V
3.3 $5%; 3.135 to 3.465 V
• 350 MHz Clock Support
• Accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL, or LVCMOS
Clock Inputs
• LVCMOS Compatible Control Inputs
• 12 LVCMOS Clock Outputs
• Synchronous Clock Select
• Output Enable to High Z State Control
• 100 ps Max. Skew Between Outputs
• Industrial Temp. Range −40°C to +85°C
• 32−pin LQFP Package
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAMS*
LQFP−32
FA SUFFIX
CASE 873A
NB3L
83948C
AWLYYWWG
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
(*Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
V_DDO
V_DD
Q0
GND
Q1
CLK_EN
D
Q2
Q
Q3
LVCMOS_CLK
1
CLK
CLK
2
Q4
Q5
CLK_SEL
Q6
Q7
V_DDO
Q8
Q9
Q10
Q11
OE
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
November, 2014 − Rev. 2
Publication Order Number:
NB3L83948C/D