NB3H63143G-D Datasheet, PDF (1/24 Pages) ON Semiconductor – 3.3 V / 2.5 V Programmable OmniClock Generator

NB3H63143G
3.3 V / 2.5 V Programmable
OmniClock Generator
with Single Ended (LVCMOS/LVTTL) and
Differential (LVPECL/LVDS/ HCSL/CML)
Outputs with Individual Output Enable
and Individual VDDO
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The NB3H63143G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
1
The device accepts fundamental mode parallel resonant crystal or a
QFN16
single ended (LVCMOS/LVTTL) reference clock as input. It
CASE 485AE
generates either three single ended (LVCMOS/LVTTL) outputs, or
one single ended output and one differential
MARKING DIAGRAM
(LVPECL/LVDS/HCSL/CML) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Individual output enable pins OE[2:0] are available to enable/disable
3H631
43Gxx
ALYWG
G
the outputs. Individual output voltage pins VDDO[2:0] are available
to independently set the output voltage of each output. Up to four
3H63143G = Specific Device Code
xx
= Specific Program Code (Default
different configurations can be written into the device memory. Two
selection pins (SEL[1:0]) allow the user to select the configuration to
A
use. Using the PLL bypass mode, it is possible to get a copy of the
L
Y
input clock on any or all of the outputs. The device can be powered
W
down using the Power Down pin (PD#). It is possible to program the
G
‘00’ for Unprogrammed Part)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
internal input crystal load capacitance and the output drive current
provided by the device. The device also has automatic gain control
(Note: Microdot may be in either location)
(crystal power limiting) circuitry which avoids the device overdriving
ORDERING INFORMATION
the external crystal.
Features
See detailed ordering and shipping information on page 23 of
this data sheet.
• Member of the OmniClock Family of Programmable
• Programmable Internal Crystal Load Capacitors
Clock Generators
• Operating Power Supply: 3.3 V ±10%, 2.5 V ±10%
• Programmable Output Drive Current for Single Ended
Outputs
• I/O Standards
• Power Saving Mode through Power Down Pin
♦ Inputs: LVCMOS/LVTTL, Fundamental Mode
• Programmable PLL Bypass Mode
Crystal
♦ Outputs: 1.8 V to 3.3 V LVCMOS/LVTTL
♦ Outputs: LVPECL, LVDS, HCSL and CML
• 3 Programmable Single Ended (LVCMOS/LVTTL)
Outputs from 8 kHz to 200 MHz
• 1 Programmable Differential Clock Output up to
200 MHz
• Programmable Output Inversion
• Programming and Evaluation Kit Available for Field
Programming and Quick Evaluation
• Temperature Range −40°C to 85°C
• Packaged in 16−pin QFN
• These are Pb−Free Devices
• Input Frequency Range
Typical Applications
♦ Crystal: 3 MHz to 50 MHz
• eBooks and Media Players
♦ Reference Clock: 3 MHz to 200 MHz
• Configurable Spread Spectrum Frequency Modulation
• Smart Wearables, Smart Phones, Portable Medical and
Industrial Equipment
Parameters (Type, Deviation, Rate)
• Individual Output Enable Pins
• Set Top Boxes, Printers, Digital Cameras and
Camcorders
• Independent Output Voltage Pins
© Semiconductor Components Industries, LLC, 2016
1
January, 2016 − Rev. 4
Publication Order Number:
NB3H63143G/D