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NB3H5150_16 Datasheet, PDF (1/19 Pages) ON Semiconductor – 2.5V / 3.3V Low Noise Multi-Rate Clock Generator | |||
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NB3H5150
2.5V / 3.3V Low Noise
Multi-Rate Clock Generator
Description
The NB3H5150 is a high performance MultiâRate Clock generator
which simultaneously synthesizes up to four different frequencies
from a single PLL using a 25 MHz input reference. The reference
frequency can be provided by a crystal, LVCMOS/LVTTL, LVPECL,
HCSL or LVDS differential signals. The REFMODE pin will select
the reference source.
Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce
user selectable frequencies of: 25 MHz, 33.33 MHz, 50 MHz,
100 MHz, 125 MHz, or 156.25 MHz and have ultraâlow noise/jitter
performance of less than 0.3 ps.
The fourth output bank (CLK4A/CLK4B) can produce the
following integer and FRACâN frequencies in pinâstrap mode:
33.33 MHz, 66.66 MHz, 100 MHz, 106.25 MHz, 125 MHz,
133.33 MHz, 155.52 MHz, 156.25 MHz or 161.1328 MHz.
Each output block can create two singleâended inâphase LVCMOS
outputs or one differential pair of LVPECL outputs.
Each of the four output blocks is independently powered by a
separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for
LVCMOS.
The serial (I2C and SMBUS) interface can be used to load register
files into the NB3H5150 to program a variety of functions including
the frequencies and output levels of each output which can be
individually enabled and disabled.
www.onsemi.com
1 32
MARKING
DIAGRAM*
1
QFN32
MN SUFFIX
CASE 485CE
NB3H
5150
AWLYYWWG
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= PbâFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 18 of
this data sheet.
Features
⢠Flexible Input Reference â 25 MHz Crystal, Oscillator,
⢠1 ps maximum RMS Phase Jitter FRACâN (CLK4)
SingleâEnded or Differential Clock
⢠Four Independent UserâProgrammable Clock
Frequencies from 25 MHz to 250 MHz
⢠Independently Configurable Outputs:
Up to Eight LVCMOS Single Ended outputs or,
Up to Four Differential LVPECL Outputs or any
combination of LVCMOS and LVPECL
⢠Flexible Input/Core and Output Power Supply
Combinations:
VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
VDDOn (Outputs) = 3.3 V ±5% or 2.5 V ±5% or
1.8 V ±5% (LVCMOS Only)
⢠Independent Power Supply for each Output Bank
⢠300 ps max Output Rise and Fall Times, LVPECL
⢠1000 ps max Output Rise and Fall Times, LVCMOS
⢠300 fs maximum RMS Phase Jitter IntergerâN
(CLK1:4) 156.25 MHz
155.52 MHz
⢠I2C / SMBus Compatible Interface
⢠â40°C to +85°C Ambient Operating Temperature
⢠Zero ppm Multiplication Error
⢠Fractional Divide Ratios for Implementing Arbitrary
FEC/InverseâFEC Ratios
⢠For Additional Pinâstrap Frequency and Output Type
Combinations, Contact ON Semiconductor Sales Office
⢠32âPin QFN, 5 mm x 5 mm
⢠This is a PbâFree Device
Applications
⢠Telecom
⢠Networking
⢠Ethernet
⢠SONET
© Semiconductor Components Industries, LLC, 2016
1
March, 2016 â Rev. 3
Publication Order Number:
NB3H5150/D
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