NB3H5150-01_16 Datasheet, PDF (1/19 Pages) ON Semiconductor – 2.5V / 3.3V Low Noise Multi-Rate Clock Generator

NB3H5150-01
2.5V / 3.3V Low Noise
Multi-Rate Clock Generator
Description
The NB3H5150−01 is a high performance Multi−Rate Clock
generator which simultaneously synthesizes up to four different
frequencies from a single PLL using a 25 MHz input reference. The
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reference frequency can be provided by a crystal, LVCMOS/LVTTL,
LVPECL, HCSL or LVDS differential signals. The REFMODE pin
will select the reference source.
MARKING
DIAGRAM*
Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce
user selectable frequencies of: 33.33 MHz, 50 MHz, 100 MHz,
125 MHz, or 156.25 MHz and have ultra−low noise/jitter performance
of less than 0.3 ps.
The fourth output bank (CLK4A/CLK4B) can produce the
1 32
1
QFN32
MN SUFFIX
CASE 485CE
NB3H
5150−01
AWLYYWWG
following integer and FRAC−N frequencies in pin−strap mode:
25 MHz, 33.33 MHz, 66.66 MHz, 100 MHz, 125 MHz, 133.33 MHz,
156.25 MHz or 161.1328 MHz.
Each output block can create two single−ended in−phase LVCMOS
outputs or one differential pair of LVPECL outputs.
Each of the four output blocks is independently powered by a
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for
LVCMOS.
The serial (I²C and SMBUS) interface can be used to load register
*For additional marking information, refer to
Application Note AND8002/D.
files into the NB3H5150−01 to program a variety of functions
including the frequencies and output levels of each output which can
ORDERING INFORMATION
be individually enabled and disabled.
See detailed ordering and shipping information on page 18 of
this data sheet.
Features
• Flexible Input Reference − 25 MHz Crystal, Oscillator,
• 1 ps maximum RMS Phase Jitter FRAC−N (CLK4)
Single−Ended or Differential Clock
161.1328 MHz
• Four Independent User−Programmable Clock
• I²C / SMBus Compatible Interface
Frequencies from 25 MHz to 250 MHz
• Independently Configurable Outputs:
Up to Eight LVCMOS Single Ended outputs or,
Up to Four Differential LVPECL Outputs or any
combination of LVCMOS and LVPECL
• Flexible Input/Core and Output Power Supply
Combinations:
VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
VDDO_n (Outputs) = 3.3 V ±5% or 2.5 V ±5% or
1.8 V ±5% (LVCMOS Only)
• Independent Power Supply for each Output Bank
• 300 ps max Output Rise and Fall Times, LVPECL
• 1000 ps max Output Rise and Fall Times, LVCMOS
• 300 fs maximum RMS Phase Jitter Interger−N
(CLK1:4) 156.25 MHz
• −40°C to +85°C Ambient Operating Temperature
• Zero ppm Multiplication Error
• Fractional Divide Ratios for Implementing Arbitrary
FEC/Inverse−FEC Ratios
• For Additional Pin−strap Frequency and Output Type
Combinations, Contact ON Semiconductor Sales Office
• 32−Pin QFN, 5 mm x 5 mm
• This is a Pb−Free Device
Applications
• Telecom
• Networking
• Ethernet
• SONET
© Semiconductor Components Industries, LLC, 2016
1
April, 2016 − Rev. 1
Publication Order Number:
NB3H5150−01/D