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NB2309A Datasheet, PDF (1/9 Pages) ON Semiconductor – 3.3 V Zero Delay Clock Buffer | |||
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NB2309A
3.3 V Zero Delay
Clock Buffer
The NB2309A is a versatile, 3.3 V zero delay buffer designed to
distribute highâspeed clocks. It accepts one reference input and drives
out nine lowâskew clocks. It is available in a 16 pin package.
The â1H version of the NB2309A operates at up to 133 MHz, and
has higher drive than the â1 devices. All parts have onâchip PLLâs that
lock to an input clock on the REF pin. The PLL feedback is onâchip
and is obtained from the CLKOUT pad.
The NB2309A has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
threeâstated. The select inputs also allow the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2309A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycleâtoâcycle jitter. The input
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
The NB2309A is available in two different configurations, as shown
in the ordering information table. The NB2309A1 is the base part. The
NB2309Ax1H* is the high drive version of the â1 and its rise and fall
times are much faster than â1 part.
Features
⢠15 MHz to 133 MHz Operating Range, Compatible with CPU and
PCI Bus Frequencies
⢠Zero Input â Output Propagation Delay
⢠Multiple LowâSkew Outputs
⢠OutputâOutput Skew Less than 250 ps
⢠DeviceâDevice Skew Less than 700 ps
⢠One Input Drives 9 Outputs, Grouped as 4 + 4 + 1
⢠Less than 200 ps CycleâtoâCycle Jitter is Compatible with PentiumR
Based Systems
⢠Test Mode to Bypass PLL
⢠Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP
⢠3.3 V Operation, Advanced 0.35 m CMOS Technology
⢠These are PbâFree Devices**
http://onsemi.com
MARKING
DIAGRAMS*
16
1
SOICâ16
D SUFFIX
CASE 751B
16
1
TSSOPâ16
DT SUFFIX
CASE 948F
16
XXXXXXXXG
AWLYWW
1
16
XXXX
XXXX
ALYWG
G
1
XXXX = Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
W, WW = Work Week
G or G = PbâFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*x = C for Commercial; I for Industrial.
**For additional information on our PbâFree strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 â Rev. 4
Publication Order Number:
NB2309A/D
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