NB100LVEP91_06 Datasheet, PDF (1/10 Pages) ON Semiconductor – 2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator

NB100LVEP91
2.5 V/3.3 V Any Level
Positive Input to
−2.5 V/−3.3 V LVNECL
Output Translator
Description
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
LVNECL output signals (−2.5 V / −3.3 V).
To accomplish the level translation the LVEP91 requires three
power rails. The V_CC pins should be connected to the positive power
supply, and the V_EE pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
V_EE and V_CC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at V_CC/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
Features
• Maximum Input Clock Frequency > 2.0 GHz Typical
• Maximum Input Data Rate > 2.0 Gb/s Typical
• 500 ps Typical Propagation Delay
• Operating Range: V_CC = 2.375 V to 3.8 V;
V_EE = −2.375 V to −3.8 V; GND = 0 V
• Q Output will Default LOW with Inputs Open or at GND
• Pb−Free Packages are Available*
http://onsemi.com
20
1
SO−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAMS*
20
NB100LVEP91
AWLYYWWG
1
24 1
24 PIN QFN
MN SUFFIX
CASE 485L
24
1 _N100
VP91
ALYWG
G
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 13
Publication Order Number:
NB100LVEP91/D