NB100LVEP224_06 Datasheet, PDF (1/10 Pages) ON Semiconductor – 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable

NB100LVEP224
2.5V/3.3V 1:24 Differential
ECL/PECL Clock Driver with
Clock Select and Output
Enable
Description
The NB100LVEP224 is a low skew 1−to−24 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The part is designed for use in low
voltage applications which require a large number of outputs to drive
precisely aligned low skew signals to their destination. The two clock
inputs are differential ECL/PECL and they are selected by the
CLK_SEL pin. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE) is synchronous
ensuring the outputs will only be enabled/disabled when they are
already in LOW state (See Figure 4).
The NB100LVEP224 guarantees low output−to−output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balanced loads on the
differential driver outputs. The wide VIHCMR specification allows
both pair of CLOCK inputs to accept LVDS levels.
The NB100LVEP224, as with most other ECL devices, can be
operated from a positive V_CC supply in LVPECL mode. This allows
the LVEP224 to be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Single−ended CLK input operation is
limited to a V_CC ≥ 3.0 V in LVPECL mode, or V_EE ≤ −3.0 V in NECL
mode. In a PECL environment, series or Thevenin line terminations
are typically used as they require no additional power supplies. For
more information on PECL terminations, designers should refer to
Application Note AND8020/D.
http://onsemi.com
MARKING
DIAGRAM*
LQFP−64
FA SUFFIX
CASE 848G
NB100
LVEP224
AWLYYWWG
64
1
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Features
• 20 ps Typical Output−to−Output Skew
• 75 ps Typical Device−to−Device Skew
• Maximum Frequency > 1 GHz
• 650 ps Typical Propagation Delay
• LVPECL Mode Operating Range:
V_CC = 2.375 V to 3.8 V with V_EE = 0 V
• NECL Mode Operating Range:
V_CC = 0 V with V_EE = −2.375 V to −3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default Low with Inputs Open or at V_EE
• Thermally Enhanced 64−Lead LQFP
• CLOCK Inputs are LVDS−Compatible; Requires
External 100 W LVDS Termination Resistor
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 7
Publication Order Number:
NB100LVEP224/D