NB100LVEP17 Datasheet, PDF (1/10 Pages) ON Semiconductor – 2.5V / 3.3V Quad Differential Driver/Receiver

NB100LVEP17
2.5V / 3.3V Quad Differential
Driver/Receiver
Description
The NB100LVEP17 is a 4-bit differential line receiver. The design
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device.
Features
• Maximum Input Clock Frequency > 2.5 GHz Typical
• Maximum Input Data Rate > 2.5 Gb/s Typical
• 250 ps Typical Propagation Delay
• Low Profile QFN Package
• PECL Mode Operating Range: V_CC = 2.375 V to 3.8 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −2.375 V to −3.8 V
• Q Output Will Default LOW with Inputs Open or at V_EE
• V_BB Output
• Pb−Free Packages are Available
http://onsemi.com
MARKING
DIAGRAMS*
TSSOP−20
DT SUFFIX
CASE 948E
24 1
24 PIN QFN
MN SUFFIX
CASE 485L
N100
VP17
ALYWG
G
24
1
N100
VP17
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 7
Publication Order Number:
NB100LVEP17/D