MUN5211T1G Datasheet, PDF (1/16 Pages) ON Semiconductor – Bias Resistor Transistor

MUN5211T1G Series
Bias Resistor Transistor
NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base--emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SC--70/SOT--323 package which is designed for low power
surface mount applications.
Features
 Simplifies Circuit Design
 Reduces Board Space
 Reduces Component Count
 The SC--70/SOT--323 package can be soldered using wave or reflow.
The modified gull--winged leads absorb thermal stress during
soldering eliminating the possibility of damage to the die.
 Available in 8 mm embossed tape and reel. Use the Device Number
to order the 7 inch/3000 unit reel.
 These Devices are Pb--Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
NPN SILICON
BIAS RESISTOR
TRANSISTORS
PIN 1
R₁
BASE
(INPUT)
R₂
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
3
1
2
SC--70/SOT--323
CASE 419
STYLE 3
MAXIMUM RATINGS (T_A = 25C unless otherwise noted)
Rating
Symbol
Value
Unit
Collector--Base Voltage
Collector--Emitter Voltage
Collector Current
THERMAL CHARACTERISTICS
V_CBO
V_CEO
I_C
50
Vdc
50
Vdc
100
mAdc
Characteristic
Symbol
Max
Unit
Total Device Dissipation
T_A = 25C
Derate above 25C
P_D 202 (Note 1) mW
310 (Note 2)
1.6 (Note 1) mW/C
2.5 (Note 2)
Thermal Resistance, Junction--to--Ambient R_θJA 618 (Note 1) C/W
403 (Note 2)
Thermal Resistance, Junction--to--Lead
R_θJL 280 (Note 1) C/W
332 (Note 2)
Junction and Storage Temperature
Range
T_J, T_stg -- 55 to +150 C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR--4 @ Minimum Pad.
2. FR--4 @ 1.0 x 1.0 inch Pad.
MARKING DIAGRAM
8x M G
G
8x = Device Code
M = Date Code*
G = Pb--Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
 Semiconductor Components Industries, LLC, 2010
1
October, 2010 -- Rev. 9
Publication Order Number:
MUN5211T1/D