MUN5111T1 Datasheet, PDF (1/12 Pages) Motorola, Inc – PNP SILICON BIAS RESISTOR TRANSISTOR

MUN5111T1 Series
Preferred Devices
Bias Resistor Transistor
PNP Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space. The device is housed in
the SC−70/SOT−323 package which is designed for low power
surface mount applications.
Features
• Pb−Free Packages are Available
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• The SC−70/SOT−323 package can be soldered using wave or reflow.
The modified gull−winged leads absorb thermal stress during
soldering eliminating the possibility of damage to the die.
• Available in 8 mm embossed tape and reel − Use the Device Number
to order the 7 inch/3000 unit reel. Replace “T1” with “T3” in the
Device Number to order the 13 inch/10,000 unit reel.
MAXIMUM RATINGS (T_A = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
V_CBO
50
Vdc
Collector-Emitter Voltage
V_CEO
50
Vdc
Collector Current
I_C
100
mAdc
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
P_D 202 (Note 1) mW
310 (Note 2)
1.6 (Note 1) _°C/W
2.5 (Note 2)
Thermal Resistance, Junction-to-Ambient
R_qJA
618 (Note 1) °C/W
403 (Note 2)
Thermal Resistance, Junction-to-Lead
R_qJL
280 (Note 1) °C/W
332 (Note 2)
Junction and Storage Temperature Range T_J, T_stg −55 to +150 °C
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
http://onsemi.com
PNP SILICON
BIAS RESISTOR
TRANSISTORS
PIN 1
R₁
BASE
(INPUT)
R₂
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
3
1
2
SC−70/SOT−323
CASE 419
STYLE 3
MARKING DIAGRAM
6x M
6x
= Specific Device Code
(See Order Info Table)
M
= Date Code
ORDERING INFORMATION
See specific ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2004
1
October, 2004 − Rev. 7
Publication Order Number:
MUN5111T1/D