MUN5111DW1T1_05 Datasheet, PDF (1/20 Pages) ON Semiconductor – Dual Bias Resistor Transistors

MUN5111DW1T1 Series
Preferred Devices
Dual Bias Resistor
Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with a
monolithic bias network consisting of two resistors; a series base resistor
and a base−emitter resistor. These digital transistors are designed to
replace a single device and its external resistor bias network. The BRT
eliminates these individual components by integrating them into a single
device. In the MUN5111DW1T1 series, two BRT devices are housed in
the SOT−363 package which is ideal for low−power surface mount
applications where board space is at a premium.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Pb−Free Packages are Available
MAXIMUM RATINGS
(T_A = 25°C unless otherwise noted, common for Q₁ and Q₂)
Rating
Symbol
Value
Unit
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
THERMAL CHARACTERISTICS
V_CBO
V_CEO
I_C
− 50
−50
−100
Vdc
Vdc
mAdc
Characteristic
(One Junction Heated)
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
P_D 187 (Note 1) mW
256 (Note 2)
1.5 (Note 1) mW/°C
2.0 (Note 2)
Thermal Resistance,
Junction-to-Ambient
R_qJA
670 (Note 1) °C/W
490 (Note 2)
Characteristic
(Both Junctions Heated)
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
P_D 250 (Note 1) mW
385 (Note 2)
2.0 (Note 1) mW/°C
3.0 (Note 2)
Thermal Resistance,
Junction-to-Ambient
R_qJA
493 (Note 1) °C/W
325 (Note 2)
Thermal Resistance,
Junction-to-Lead
R_qJL
188 (Note 1) °C/W
208 (Note 2)
Junction and Storage Temperature Range T_J, T_stg −55 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
© Semiconductor Components Industries, LLC, 2005
1
September, 2005 − Rev. 6
http://onsemi.com
(3)
(2)
(1)
R₁
R₂
Q₁
Q₂
R₂
R₁
(4)
(5)
(6)
1
SOT−363
CASE 419B
STYLE 1
MARKING DIAGRAM
6
xx M G
G
1
xx = Device Code (Refer to page 2)
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the table on
page 2 of this data sheet.
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MUN5111DW1T1/D