MTV10N100E Datasheet, PDF (1/11 Pages) Motorola, Inc – TMOS POWER FET 10 AMPERES 1000 VOLTS RDS(on) = 1.3 OHM

MTV10N100E
Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect
Transistor
D³PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
The D³PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor. This
allows it to be used in applications that require surface mount
components with higher power and lower R_DS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to provide
enhanced voltage−blocking capability without degrading performance
over time. In addition, this advanced TMOS E−FET is designed to
withstand high energy in the avalanche and commutation modes. The
new energy efficient design also offers a drain−to−source diode with a
fast recovery time. Designed for high voltage, high speed switching
applications in surface mount PWM motor controls and both ac−dc and
dc−dc power supplies. These devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I_DSS and V_DS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured − Not Sheared
• Specifically Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm, 13−inch/500 Unit Tape & Reel, Add −RL Suffix
to Part Number
http://onsemi.com
TMOS POWER FET
10 AMPERES, 1000 VOLTS
R_DS(on) = 1.3 W
D³PAK Surface Mount
CASE 433−01
Style 2
D
N−Channel
G
®
S
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
© Semiconductor Components Industries, LLC, 2006
1
August, 2006 − Rev. 1
Publication Order Number:
MTV10N100E/D