MTP1N100E Datasheet, PDF (1/7 Pages) Motorola, Inc – TMOS POWER FET 1.0 AMPERES 1000 VOLTS RDS(on) = 9.0 OHM

MTP1N100E
Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect
Transistor
High−Performance Silicon−Gate CMOS
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I_DSS and V_DS(on) Specified at Elevated Temperature
http://onsemi.com
TMOS POWER FET
1.0 AMPERES, 1000 VOLTS
R_DS(on) = 9.0 W
TO−220AB
CASE 221A−06
Style 5
D
®
G
MAXIMUM RATINGS (T_C = 25°C unless otherwise noted)
Rating
Symbol
Value
S
Unit
Drain−Source Voltage
Drain−Gate Voltage (R_GS = 1.0 MΩ)
Gate−Source Voltage — Continuous
Gate−Source Voltage — Non−Repetitive (t_p ≤ 10 ms)
V_DSS
V_DGR
V_GS
V_GSM
1000
Vdc
1000
Vdc
± 20
Vdc
± 40
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (t_p ≤ 10 μs)
Total Power Dissipation
Derate above 25°C
I_D
1.0
Adc
I_D
0.8
I_DM
3.0
Apk
P_D
75
Watts
0.6
W/°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting T_J = 25°C
(V_DD = 100 Vdc, V_GS = 10 Vdc, I_L = 3.0 Apk, L = 10 mH, R_G = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T_J, T_stg
E_AS
R_θJC
R_θJA
T_L
−55 to 150
45
1.67
62.5
260
°C
mJ
°C/W
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
© Semiconductor Components Industries, LLC, 2006
1
August, 2006 − Rev. 3
Publication Order Number:
MTP1N100E/D