MTD5N25E Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 5.0 AMPERES 250 VOLTS RDS(on) = 1.0 OHM

MTD5N25E
TMOS E−FET.™
Power Field Effect
Transistor
DPAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
This advanced TMOS E−FET is designed to withstand high energy
in the avalanche and commutation modes. The new energy efficient
design also offers a drain−to−source diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I_DSS and V_DS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13−inch/2500
Unit Tape & Reel, Add −T4 Suffix to Part Number
http://onsemi.com
TMOS POWER FET
5.0 AMPERES, 250 VOLTS
R_DS(on) = 1.0 W
DPAK
CASE 369A−13
Style 2
D
®
G
S
MAXIMUM RATINGS (T_C = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−Source Voltage
Drain−Gate Voltage (R_GS = 1.0 MΩ)
Gate−Source Voltage — Continuous
— Non−repetitive (t_p ≤ 10 ms)
V_DSS
250
Vdc
V_DGR
250
Vdc
V_GS
± 20
Vdc
V_GSM
± 40
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (t_p ≤ 10 μs)
I_D
5.0
Adc
I_D
3.2
I_DM
15
Apk
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
P_D
50
Watts
0.4
W/°C
Total Power Dissipation @ T_A = 25°C, when mounted to minimum recommended pad size
1.75
Watts
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting T_J = 25°C
(V_DD = 80 Vdc, V_GS = 10 Vdc, I_L = 7.5 Apk, L = 3.0 mH, R_G = 25 Ω)
T_J, T_stg
−55 to 150
°C
E_AS
84
mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
— Junction to Ambient, when mounted to minimum recommended pad size
R_θJC
R_θJA
R_θJA
2.50
°C/W
100
71.4
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T_L
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
© Semiconductor Components Industries, LLC, 2006
1
August, 2006 − Rev. 2
Publication Order Number:
MTD5N25E/D