MC74VHCT74A_06 Datasheet, PDF (1/6 Pages) ON Semiconductor – Dual D−Type Flip−Flop with Set and Reset

MC74VHCT74A
Dual D−Type Flip−Flop
with Set and Reset
The MC74VHCT74A is an advanced high speed CMOS D−type
flip−flop fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output
during the positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT74A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V_CC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
• High Speed: f_max = 60 MHz (Typ) at V_CC = 5.0 V
• Low Power Dissipation: I_CC = 2 mA (Max) at T_A = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 4.5 V to 5.5 V Operating Range
• Low Noise: V_OLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 128 FETs or 32 Equivalent Gates
• Pb−Free Packages are Available
RD1 ¹
D1 ²
3
CP1
SD1 ⁴
13
RD2
5
Q1
D2 ¹²
6
Q1
11
CP2
10
SD2
Figure 2. Logic Diagram
9
Q2
8
Q2
© Semiconductor Components Industries, LLC, 2006
1
July, 2006 − Rev. 5
http://onsemi.com
MARKING DIAGRAMS
14
SOIC−14
D SUFFIX
1
CASE 751A
VHCT74AG
AWLYWW
1
14
TSSOP−14
DT SUFFIX
1 _{CASE 948G}
VHCT
74A
ALYWG
G
A
= Assembly Location ¹
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
RD1 1
D1 2
CP1 3
SD1 4
Q1 5
Q1 6
14 V_CC
13 RD2
12 D2
11 CP2
10 SD2
9 Q2
GND 7
8 Q2
Figure 1. Pin Assignment
FUNCTION TABLE
Inputs
SD RD CP D
Outputs
QQ
LH
HL
LL
HH
HH
HH
HH
HH
XX
HL
XX
LH
X X H* H*
H
HL
L
LH
L X No Change
H X No Change
X No Change
*Both outputs will remain high as long as Set and Reset
are low, but the output states are unpredictable if Set
and Reset go high simultaneously.
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
Publication Order Number:
MC74VHCT74A/D