MC74VHCT540A Datasheet, PDF (1/8 Pages) ON Semiconductor – Octal Bus Buffer Inverting

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal Bus Buffer
Inverting
The MC74VHCT540A is an advanced high speed CMOS inverting octal
bus buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHCT540A features inputs and outputs on opposite sides of the
package and two AND–ed active–low output enables. When either OE1 or
OE2 are high, the terminal outputs are in the high impedance state.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT540A input and output (when disabled) structures provide
protection when voltages between 0V and 5.5V are applied, regardless of
the supply voltage. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 3.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 1.2V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 124 FETs or 31 Equivalent Gates
DATA
INPUTS
OUTPUT
ENABLES
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
OE1 ¹
OE2 ¹⁹
LOGIC DIAGRAM
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
INVERTING
OUTPUTS
13
Y6
12
Y7
11
Y8
MC74VHCT540A
DW SUFFIX
20–LEAD SOIC WIDE PACKAGE
CASE 751D–05
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
ORDERING INFORMATION
MC74VHCTXXXADW SOIC WIDE
MC74VHCTXXXADT TSSOP
MC74VHCTXXXAM SOIC EIAJ
PIN ASSIGNMENT
OE1 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 VCC
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
FUNCTION TABLE
Inputs
OE1 OE2
A
L
L
L
L
L
H
H
X
X
X
H
X
Output Y
H
L
Z
Z
4/99
© Motorola, Inc. 1999
1
REV 0