MC74VHCT245A Datasheet, PDF (1/6 Pages) ON Semiconductor – Octal Bus Transceiver

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal Bus Transceiver
The MC74VHCT245A is an advanced high speed CMOS octal bus
transceiver fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
It is intended for two–way asynchronous communication between data
buses. The direction of data transmission is determined by the level of the
DIR input. The output enable pin (OE) can be used to disable the device, so
that the buses are effectively isolated.
All inputs are equipped with protection circuits against static discharge.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT245A input and output (when disabled) structures provide
protection when voltages between 0V and 5.5V are applied, regardless of
the supply voltage. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: tPD = 4.9ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 4.5V to 5.5V Operating Range
• Low Noise: VOLP = 1.6V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 304 FETs or 76 Equivalent Gates
APPLICATION NOTES
1. Do not force a signal on an I/O pin when it is an active output, damage may
occur.
2. All floating (high impedence) input or I/O pins must be fixed by means of
pull up or pull down resistors or bus terminator ICs.
A
DATA
PORT
A1 ²
A2 ³
A3 ⁴
A4 ⁵
A5 ⁶
A6 ⁷
A7 ⁸
A8 ⁹
DIR ¹
OE ¹⁹
LOGIC DIAGRAM
18 _B1
17 _B2
16 _B3
15 _B4
14 _B5
13 _B6
12 _B7
11 _B8
B
DATA
PORT
MC74VHCT245A
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
ORDERING INFORMATION
MC74VHCTXXXADW SOIC
MC74VHCTXXXADT TSSOP
MC74VHCTXXXAM
SOIC EIAJ
PIN ASSIGNMENT
DIR 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 VCC
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
FUNCTION TABLE
Control Inputs
OE DIR
Operation
L
L Data Tx from Bus B to Bus A
L
H Data Tx from Bus A to Bus B
H
X Buses Isolated (High–Z State)
6/97
© Motorola, Inc. 1997
1
REV 0