MC74VHCT138A Datasheet, PDF (1/6 Pages) ON Semiconductor – 3-to-8 Line Decoder

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3-to-8 Line Decoder
The MC74VHCT138A is an advanced high speed CMOS 3–to–8 decoder
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 – A2)
determine which one of the outputs (Y0 – Y7) will go Low. When enable input
E3 is held Low or either E2 or E1 is held High, decoding function is inhibited
and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade
connection and for use as an address decoder for memory systems.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because they have full 5V
CMOS level output swings.
The VHCT138A input structures provide protection when voltages
between 0V and 5.5V are applied, regardless of the supply voltage. The
output structures also provide protection when VCC = 0V. These input and
output structures help prevent device destruction caused by supply voltage
– input/output voltage mismatch, battery backup, hot insertion, etc.
• High Speed: tPD = 7.6ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 4.5V to 5.5V Operating Range
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
MC74VHCT138A
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01
ORDERING INFORMATION
MC74VHCTXXXAD SOIC
MC74VHCTXXXADT TSSOP
MC74VHCTXXXAM SOIC EIAJ
PIN ASSIGNMENT
A0 1
A1 2
A2 3
E1 4
E2 5
E3 6
Y7 7
GND 8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
FUNCTION TABLE
Inputs
Outputs
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H XXX HHH HHHH H
X H X XXX HHH HHHH H
L X X XXX HHH HHHH H
H L L LLL LHHHHHHH
H L L LLHH L HHHHHH
H L L LHL HH L HHHHH
H L L LHH H H H L H H H H
H L L HLL HHHH L HHH
H L L HLHHHHHH L HH
H L L HHL H H H H H H L H
H L L HHH H H H H H H H L
H = high level (steady state); L = low level (steady state); X = don’t care
SELECT
INPUTS
ENABLE
INPUTS
A0 ¹
A1 ²
A2 ³
E3 ⁶
5
E2
E1 ⁴
15 _Y0
14 _Y1
13 _Y2
12 _Y3
11 _Y4
10
Y5
9 _Y6
7
Y7
ACTIVE–LOW
OUTPUTS
LOGIC DIAGRAM
6/97
© Motorola, Inc. 1997
1
REV 0