MC74VHCT02A Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad 2-Input NOR Gate

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input NOR Gate
The MC74VHCT02A is an advanced high speed CMOS 2–input NOR gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT02A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC = 0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 3.6ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 40 FETs or 10 Equivalent Gates
2
A1
3
B1
5
A2
6
B2
8
A3
9
B3
11
A4
12
B4
LOGIC DIAGRAM
1
Y1
4
Y2
Y=A+B
10
Y3
13
Y4
MC74VHCT02A
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
ORDERING INFORMATION
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
SOIC
TSSOP
SOIC EIAJ
PIN ASSIGNMENT
Y1 1
A1 2
B1 3
Y2 4
A2 5
B2 6
GND 7
14 VCC
13 Y4
12 B4
11 A4
10 Y3
9 B3
8 A3
4/99
© Motorola, Inc. 1999
FUNCTION TABLE
Inputs
A
B
L
L
L
H
H
L
H
H
Output
Y
H
L
L
L
1
REV 0