MC74VHC1GT50 Datasheet, PDF (1/8 Pages) ON Semiconductor – Noninverting Buffer / CMOS Logic Level Shifter

MC74VHC1GT50
Noninverting Buffer /
CMOS Logic Level Shifter
with TTL-Compatible Inputs
The MC74VHC1GT50 is a single gate noninverting buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL- type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic- level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high- voltage power supply.
The MC74VHC1GT50 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT50 to be used to interface high voltage to low
voltage circuits. The output structures also provide protection when
V_CC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage - input/output voltage mismatch,
battery backup, hot insertion, etc.
• Designed for 1.65 V to 5.5 V_CC Operation
• High Speed: t_PD = 3.5 ns (Typ) at V_CC = 5 V
• Low Power Dissipation: I_CC = 1 mA (Max) at T_A = 25°C
• TTL-Compatible Inputs: V_IL = 0.8 V; V_IH = 2.0 V, V_CC = 5 V
• CMOS- Compatible Outputs: V_OH > 0.8 V_CC; V_OL < 0.1 V_CC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 104; Equivalent Gates = 26
NC 1
IN A 2
5 V_CC
http://onsemi.com
MARKING
DIAGRAMS
SC-88A / SOT-353/SC-70
DF SUFFIX
VL^d
CASE 419A
Pin 1
d = Date Code
TSOP-5/SOT-23/SC-59
DT SUFFIX
VL^d
CASE 483
Pin 1
d = Date Code
PIN ASSIGNMENT
1
2
3
4
5
FUNCTION TABLE
A Input
L
H
NC
IN A
GND
OUT Y
V_CC
Y Output
L
H
GND 3
4 OUT Y
Figure 1. Pinout (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
IN A
1
OUT Y
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2003
1
March, 2003 - Rev. 11
Publication Order Number:
MC74VHC1GT50/D