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MC74VHC1GT126_09 Datasheet, PDF (1/6 Pages) ON Semiconductor – Noninverting Buffer / CMOS Logic Level Shifter with LSTTL.Compatible Inputs | |||
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MC74VHC1GT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTLâCompatible Inputs
The MC74VHC1GT126 is a single gate noninverting 3âstate buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC1GT126 requires the 3âstate control input (OE) to be
set Low to place the output into the high impedance state.
The device input is compatible with TTLâtype input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logicâlevel translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the highâvoltage power supply.
The MC74VHC1GT126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT126 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage â input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
⢠High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
⢠Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
⢠TTLâCompatible Inputs: VIL = 0.8 V; VIH = 2 V
⢠CMOSâCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
⢠Power Down Protection Provided on Inputs and Outputs
⢠Balanced Propagation Delays
⢠Pin and Function Compatible with Other Standard Logic Families
⢠Chip Complexity: FETs = 62; Equivalent Gates = 16
⢠NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECâQ100
Qualified and PPAP Capable
⢠These Devices are PbâFree and are RoHS Compliant
OE 1
IN A 2
GND 3
5 VCC
4 OUT Y
Figure 1. Pinout (Top View)
OE
OUT Y
IN A
Figure 2. Logic Symbol
http://onsemi.com
MARKING
DIAGRAMS
5
1
SCâ88A / SOTâ353 / SCâ70
DF SUFFIX
CASE 419A
5
W3 M G
G
1
5
1
TSOPâ5 / SOTâ23 / SCâ59
DT SUFFIX
CASE 483
5
W3 M G
G
1
W3 = Device Code
M = Date Code*
G = PbâFree Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
PIN ASSIGNMENT
1
OE
2
IN A
3
GND
4
OUT Y
5
VCC
A Input
L
H
X
FUNCTION TABLE
OE Input
Y Output
H
L
H
H
L
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
May, 2012 â Rev. 15
Publication Order Number:
MC74VHC1GT126/D
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